1. Field of the Invention
This invention relates in general to a semiconductor component and its manufacturing method, and more particularly to a multi-level metallization and interconnection component and its manufacturing method.
2. Description of the Related Art
As the level of integration for integrated circuits increases, the number of interconnects necessary for linking up devices increases, too. Therefore, design employing two or more metallic layers is gradually becoming the norm in the fabrication of integrated circuits. When the level of integration is further increased a high production yield and good reliability is difficult to get. Damascene processing method is a fabrication technique that involves the creation of interconnect lines by first etching a trench in a planar dielectric layer, and then filling that trench with metal. The method is capable of introducing copper metal which is not easily etched into the semiconductor device. Therefore, this method is the best choice in the manufacturing industry for sub-quarter micron interconnects.
Conventional damascene processing technique has a number of problems. For example, depth of trench lines is hard to control, profile of via sidewall is difficult to standardize and the processing window is quite narrow.
FIG. 1A to FIG. 1D are cross-sectional views showing the manufacturing steps of a conventional dual damascene processing method. As shown in FIG. 1A, an insulator layer 102 is deposited over a semiconductor substrate 100. Then, a mask is used to define the pattern of the interconnection on the insulator layer 102. An etching process is carried out for forming a trench 104 in the insulator layer 102.
Next, referring to FIG. 1B, a thick photoresist layer 106 is formed over the insulator layer 102, filling in the trench 104. Defining and etching processes are then performed to expose the surface of the insulator layer 102 in the trench 104 so as to form a first via 108.
Then, as shown in FIG. 1C, an etching process is performed to remove parts of the insulator layer 102 exposed in the first via 108 and to form a second via 108', exposing the semiconductor substrate 100.
Next, the photoresist layer 106 is removed as shown in FIG. 1D so as to form a third via 110 with two different of widths. A conductive layer (not shown) is formed over the entire structure; thereafter a polishing process is performed to remove the conductive layer over the insulator layer 102. This completes the forming of the dual damascene structure.
The method of manufacturing the dual damascene according the conventional method described above is not without flaws. After the trench is formed, it is necessary to perform a photolithography step for forming the first via. And, the width of the first via is smaller than the trench, therefore misalignment of the pattern occurres during the defining procedure. Furthermore, it is difficult to etch and form the via owing to the larger aspect ratio of the second via.
FIG. 2A to FIG. 2E are cross-sectional views showing the manufacturing steps of another conventional dual damascene processing method. As shown in FIG. 2A, an insulator layer 202 is deposited over a semiconductor substrate 200. Then, a mask is used to define the pattern of the interconnection on the insulator layer 202. An etching process is carried out to form a trench 204 within the insulator layer 202 and expose the surface of the semiconductor substrate 200.
Next, referring to FIG. 2B, a layer of photoresist 206 is formed over the insulator layer 202, filling the via 204. Then, as shown in FIG. 2C, a mask is used to define the pattern of the trench 208 within the photoresist layer 206, and the undesired photoresist 206 is removed to expose parts of the insulator layer 202. The photoresist plug 206' remains in the via 204. The width of the trench 208 is larger than the via 204.
Referring to FIG. 2D, an etching step is then performed on the insulator layer 202 so as to form a trench 208' by using the trench pattern 208 within the photoresist layer 206.
Next, as shown in FIG. 2E, the photoresist layer 206 and photoresist plug 206' are removed. A conductive layer (not shown) is formed on the entire structure; thereafter a polishing process is performed to remove the conductive layer over the insulator layer 202. This completes the forming of the dual damascene structure.
The method described above still has drawbacks. For example, there is no etching stop layer within the insulator layer, therefore it may be over-etched during the trench etching operation. As the level of integration for integrated circuits increases, it is harder and harder to remove the photoresist plug within the via. Furthermore, this method also uses several photolithographic and etching steps which are accompanied by misalignment during the via and trench formation procedures.